There are a number of challenges that scaling of conventional planar metal-oxide-semiconductor field-effect transistors (MOSFETs) are faced with. For example, threshold swing degradation, large drain-induced barrier lowering (DIBL), device characteristics fluctuations, and leakage are among the most common problems that may be addressed by 3-D device structures. Fin field-effect transistors (FinFETs) are 3-D device structures that can be used in nano-scale complementary metal-oxide-semiconductor (CMOS) and high-density memory applications.
FinFET devices are divided into two categories, bulk finFETs and silicon-on-insulator (SOI) finFETs. In bulk finFET devices, which are more common in 14 nm and/or 16 nm technology, the fin can be formed on the bulk silicon (e.g., silicon substrate). The bulk finFET can be produced at low cost, low defect density, high heat transfer to substrate, and good process control. Bulk finFETs with lateral double-diffused MOS (LDMOS) structures, which are mostly used in RF power amplifiers, can provide a high breakdown voltage (e.g., between drain and source terminals). The high breakdown voltage is achieved, for example, by a charge carrier (e.g., electron) flow path that passes through a depletion region.